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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. MAX7060 280mhz to 450mhz programmable ask/fsk transmitter 19-5096; rev 0; 2/10 general description the MAX7060 frequency and power-programmable ask/fsk transmitter operates at 280mhz to 450mhz frequencies. this device incorporates a fully integrated fractional-n synthesizer, which allows the user to set the rf operating frequency to a large fraction of the 280mhz to 450mhz frequency range with a single crystal. for example, the MAX7060 can be tuned from 285mhz to 420mhz with a 15mhz crystal. the rf output power is user-controlled between +14dbm and -14dbm, with a 5v supply or with battery voltages as low as 3.2v. at the minimum specified battery voltage of 2.1v, the rf output power-control range is between +10dbm and -14dbm. to maintain a good output power match across a broad range of frequencies, the MAX7060 also contains a pro - grammable matching capacitor connected in parallel with the power amplifier (pa) output. ask modulation is accomplished by switching the pa on and off, so excellent modulation (on/off) ratios are achieved. ask amplitude shaping is available to reduce the width of the transmission spectrum. fsk modula - tion is accomplished by changing the coefficients of the high-resolution fractional-n synthesizer, so fsk deviation is extremely accurate. data rates up to 50kbps manchester coded for ask and 70kbps manchester coded for fsk can be maintained while still satisfying regulatory emission-bandwidth standards. the full set of configuration functions are handled by an on-chip serial peripheral interface (spi k ). there is also a manual mode where a limited number of settings can be made directly through selected pins. the startup time is very short, and data can be transmit - ted 250 f s after the enable command. the MAX7060 operates from a 2.1v to 3.6v supply, or internal regula - tors can be used for supply voltages between 4.5v and 5.5v. the standby current in the 3v mode is 400na at room temperature, and can be reduced to 5na using the low-power shutdown (lshdn) pin. the MAX7060 is available in a 24-pin (4mm x 4mm) thin qfn package and is specified for the automotive tem - perature range from -40 n c to +125 n c. features s fully integrated, fast fractional-n pll 280mhz to 450mhz rf frequency frequency range 100% tested at +125 n c < 250s startup time adjustable fsk mark and space frequencies ultra-clean fsk modulation 50kbps manchester data rate ask 70kbps manchester data rate fsk s programmable power amplifier +14dbm tx power with 5v supply +10dbm tx power at 2.1v supply 28db power-control range in 1db steps s tunable pa matching capacitor s control through spi or manual settings s low shutdown current for 2.1v to 3.6v supply 400na standby current, power-on-reset (por) active 5na shutdown current, por inactive s supply flexibility 2.1v to 3.6v single-supply operation or 4.5v to 5.5v supply operation with internal regulators s 24-pin (4mm x 4mm) tqfn package s fcc part 15, etsi en 300 220 compliant* * etsi compliance up to +6dbm eirp. applications garage-door openers remote controls home and industrial automation sensor networks security systems ordering information spi is a trademark of motorola, inc. + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part. * ep = exposed pad. part temp range pin-package MAX7060atg+ -40 n c to +125 n c 24 tqfn-ep* MAX7060atg/v+ -40 n c to +125 n c 24 tqfn-ep*
2 ______________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. gpovdd, v dd5 to gnd ....................................... -0.3v to +6.0v dvdd, pavdd, and avdd to gnd ..................... -0.3v to +4.0v enable, sclk_pwr0, sdi_pwr1, din, cs _dev, lshdn, freq0, freq1, freq2, gpo1, and gpo2_mod to gnd ..................... -0.3v to (v dd5 + 0.3v) paout, rout, and pavout to gnd ....................... -0.3v to (pavdd + 0.3v) xtal1 and xtal2 to gnd .................... -0.3v to (avdd + 0.3v) continuous power dissipation (t a = +70 n c) 24-pin thin qfn (derate 14.7mw/ n c above +70 n c) ............................ 1167mw operating temperature range ........................ -40 n c to +125 n c storage temperature range ............................ -60 n c to +150 n c lead temperature (soldering, 10s) ............................... +300 n c soldering temperature (reflow) ...................................... +260 n c dc electrical characteristics (5v operation) ( typical application circuit , 50 i system impedance, tuned for 315mhz to 434mhz operation. v dd5 = v gpovdd = 4.5v to 5.5v, f rf = 280mhz to 450mhz, f xtal = 15mhz to 16mhz, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at v dd5 = v gpovdd = +5v, t a = +25 n c, pa matched for optimum output power, unless otherwise noted. all min and max values are 100% tested at t a = +125 n c and guaranteed by design and characterization over temperature, unless otherwise noted.) absolute maximum ratings parameter symbol conditions min typ max units supply voltage v dd 4.5 5 5.5 v regulated analog supply voltage avdd 3.2 v active supply current i dd pll on, pa off f rf = 315mhz 4.7 6.0 ma f rf = 433.92mhz 5.3 6.9 pll on, pa on, data at 50% duty cycle (ask), +10dbm (papwr = 0x19) output power (notes 1, 2) f rf = 315mhz 12.5 f rf = 433.92mhz 14.2 pll on, pa on, data at 100% duty cycle, +10dbm (papwr = 0x19) output power (note 1) f rf = 315mhz 19 26 f rf = 433.92mhz 25 31.6 pll on, pa on, data at 100% duty cycle, max (papwr = 0x1e) output power (note 1) f rf = 315mhz 28 f rf = 433.92mhz 34 standby current i stdby v enable < v il , v lshdn < v il t a = +25 n c 1.1 f a t a = +85 n c 1.3 t a = +125 n c 3.8 6.1 digital i/o input high threshold v ih 0.9 x v dvdd v input low threshold v il 0.1 x v dvdd v
_______________________________________________________________________________________ 3 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter dc electrical characteristics (3v operation) ( typical application circuit , 50 i system impedance, tuned for 315mhz to 434mhz operation. v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.1v to 3.6v, f rf = 280mhz to 450mhz, f xtal = 15mhz to 16mhz, t a = -40 n c to +125 n c, unless oth - erwise noted. typical values are at v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.7v, t a = +25 n c, pa matched for optimum output power, unless otherwise noted. all min and max values are 100% tested at t a = +125 n c and guaranteed by design and characterization over temperature, unless otherwise noted.) dc electrical characteristics (5v operation) (continued) ( typical application circuit , 50 i system impedance, tuned for 315mhz to 434mhz operation. v dd5 = v gpovdd = 4.5v to 5.5v, f rf = 280mhz to 450mhz, f xtal = 15mhz to 16mhz, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at v dd5 = v gpovdd = +5v, t a = +25 n c, pa matched for optimum output power, unless otherwise noted. all min and max values are 100% tested at t a = +125 n c and guaranteed by design and characterization over temperature, unless otherwise noted.) parameter symbol conditions min typ max units input pulldown sink current i ih 6 f a input pullup source current i il 5 f a output-voltage high v oh i sink = 100 f a (gpo1 and gpo2_mod, gp1bst bit = 0) v gpovdd - 0.10 v i sink = 200 f a (gpo1), boost = on (gp1bst bit = 1) v gpovdd - 0.14 output-voltage low v ol i source = 100 f a (gpo1 and gpo2_mod, gp1bst bit = 0) 0.10 v i source = 200 f a (gpo1), boost = on (gp1bst bit = 1) 0.14 parameter symbol conditions min typ max units supply voltage v dd 2.1 2.7 3.6 v active supply current i dd pll on, pa off f rf = 315mhz 4.2 6.2 ma f rf = 433.92mhz 4.8 7.2 pll on, pa on, data at 50% duty cycle (ask), +10dbm (papwr = 0x19) output power (notes 1, 2) f rf = 315mhz 11 f rf = 433.92mhz 13 pll on, pa on, data at 100% duty cycle, +10dbm (papwr = 0x19) output power (note 1) f rf = 315mhz 17.2 27 f rf = 433.92mhz 22 31.6 standby current i stdby v enable < v il , v lshdn < v il t a = +25 n c 0.4 f a t a = +85 n c 0.5 t a = +125 n c 2.5 6.0 shutdown current i shdn v enable < v il , v lshdn > v ih t a = +25 n c 0.005 f a t a = +85 n c 0.3 t a = +125 n c 2.6 6.0
4 ______________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter dc electrical characteristics (3v operation) (continued) ( typical application circuit , 50 i system impedance, tuned for 315mhz to 434mhz operation. v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.1v to 3.6v, f rf = 280mhz to 450mhz, f xtal = 15mhz to 16mhz, t a = -40 n c to +125 n c, unless oth - erwise noted. typical values are at v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.7v, t a = +25 n c, pa matched for optimum output power, unless otherwise noted. all min and max values are 100% tested at t a = +125 n c and guaranteed by design and characterization over temperature, unless otherwise noted.) ac electrical characteristics (5v operation) ( typical application circuit , 50 i system impedance, tuned for 315mhz to 434mhz operation, v dd5 = v gpovdd = 4.5v to 5.5v, f rf = 280mhz to 450mhz, f xtal = 15mhz to 16mhz, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at v dd5 = v gpovdd = +5v, t a = +25 n c, pa matched for optimum output power, unless otherwise noted. all min and max values are 100% tested at t a = +125 n c and guaranteed by design and characterization over temperature, unless otherwise noted.) parameter symbol conditions min typ max units digital i/o input high threshold v ih 0.9 x v dvdd v input low threshold v il 0.1 x v dvdd v input pulldown sink current i ih 5 f a input pullup source current i il 1.3 f a output-voltage high v oh i sink = 100 f a (gpo1 and gpo2_mod, gp1bst bit = 0) v gpovdd - 0.10 v i sink = 200 f a (gpo1) boost = on (gp1bst bit = 1) v gpovdd - 0.14 output-voltage low v ol i source = 100 f a (gpo1 and gpo2_mod, gp1bst bit = 0) 0.10 v i source = 200 f a (gpo1) boost = on (gp1bst bit = 1) 0.14 parameter symbol conditions min typ max units general characteristics frequency range 280 450 mhz power-on time t on enable low-to-high transition, frequency settled to within 50khz of the desired carrier (includes time for v pavout to settle) 130 f s enable low-to-high transition, frequency settled to within 5khz of the desired carrier (includes time for v pavout to settle) 185 maximum data rate (papwr = 0x1e) ask mode (no shaping) manchester encoded 50 kbps nonreturn to zero 100 fsk mode manchester encoded 70 nonreturn to zero 140
_______________________________________________________________________________________ 5 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter ac electrical characteristics (5v operation) (continued) ( typical application circuit , 50 i system impedance, tuned for 315mhz to 434mhz operation, v dd5 = v gpovdd = 4.5v to 5.5v, f rf = 280mhz to 450mhz, f xtal = 15mhz to 16mhz, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at v dd5 = v gpovdd = +5v, t a = +25 n c, pa matched for optimum output power, unless otherwise noted. all min and max values are 100% tested at t a = +125 n c and guaranteed by design and characterization over temperature, unless otherwise noted.) parameter symbol conditions min typ max units carrier-frequency switching time time from end of spi write or change of freq0, freq1, or freq2 pins, to frequency settled to within 5khz of desired carrier 60 f s pll vco gain k vco 340 mhz/v pll phase noise f rf = 315mhz 10khz offset -78 dbc/hz 1mhz offset -97 f rf = 433.92mhz 10khz offset -74 1mhz offset -97 loop bandwidth 300 khz reference frequency input level 500 mv p-p frequency divider range 19 28 frequency deviation (fsk) q 2 q 100 khz crystal oscillator crystal frequency f xtal 15 to 16 mhz crystal load capacitance (note 3) 10 pf power amplifier output transmit power (note1) p out maximum output transmit power: papwr = 0x1e +14.5 dbm minimum output transmit power: papwr = 0x00 -14 power-control step size 0.95 db modulation depth (note 1) 70 db maximum carrier harmonics (note 1) -24 dbc reference spur -42 dbc paout capacitor tuning range 0 to 7.75 pf
6 ______________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter ac electrical characteristics (3v operation) ( typical application circuit , 50 i system impedance, tuned for 315mhz to 434mhz operation. v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.1v to 3.6v, f rf = 280mhz to 450mhz, f xtal = 15mhz to 16mhz, t a = -40 n c to +125 n c, unless oth - erwise noted. typical values are at v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.7v, t a = +25 n c, pa matched for optimum output power, unless otherwise noted. all min and max values are 100% tested at t a = +125 n c and guaranteed by design and characterization over temperature, unless otherwise noted.) parameter symbol conditions min typ max units general characteristics frequency range 280 450 mhz power-on time t on enable low-to-high transition, frequency settled to within 50khz of the desired car - rier (includes time for v pavout to settle) 120 f s enable low-to-high transition, frequency settled to within 5khz of the desired carrier (includes time for v pavout to settle) 200 maximum data rate (papwr = 0x19) ask mode (no shaping) manchester encoded 50 kbps nonreturn to zero 100 fsk mode manchester encoded 70 nonreturn to zero 140 carrier-frequency switching time time from end of spi write or change of freq0, freq1, or freq2 pins, to frequency settled to within 5khz of desired carrier 60 f s pll vco gain k vco 340 mhz/v pll phase noise f rf = 315mhz 10khz offset -78 dbc/hz 1mhz offset -97 f rf = 433.92mhz 10khz offset -74 1mhz offset -97 loop bandwidth 300 khz reference frequency input level 500 mv p-p frequency divider range 19 28 crystal oscillator frequency deviation (fsk) q 2 q 100 khz crystal frequency f xtal 15 to 16 mhz frequency pulling by power supply 4 ppm/v crystal load capacitance (note 3) 10 pf power amplifier output transmit power (note1) p out v pavdd = 2.1v, papwr = 0x1e +10 dbm v pavdd = 3.6v, papwr = 0x1e +15 papwr = 0x00 -14.5 power-control step size 0.95 db modulation depth (note 1) 70 db
_______________________________________________________________________________________ 7 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter ac electrical characteristics (3v operation) (continued) ( typical application circuit , 50 i system impedance, tuned for 315mhz to 434mhz operation. v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.1v to 3.6v, f rf = 280mhz to 450mhz, f xtal = 15mhz to 16mhz, t a = -40 n c to +125 n c, unless oth - erwise noted. typical values are at v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.7v, t a = +25 n c, pa matched for optimum output power, unless otherwise noted. all min and max values are 100% tested at t a = +125 n c and guaranteed by design and characterization over temperature, unless otherwise noted.) serial peripheral interface (spi) timing characteristics (spi timing characteristics are valid for both 3v and 5v modes. spi timing is production tested at worst-case temperature and supply with a clock frequency of 3mhz.) note 1: supply current and output power are greatly dependent on board layout and paout match. note 2: 50% duty cycle at 10khz ask data (manchester coded). note 3: dependent on pcb trace capacitance. parameter symbol conditions min typ max units maximum carrier harmonics (note 1) -24 dbc reference spur -43 dbc paout capacitor tuning range 0 to 7.75 pf parameter symbol conditions min typ max units minimum sclk_pwr0 low to falling-edge of cs _dev setup time t sc 30 ns minimum cs _dev low to rising edge of sclk_pwr0 setup time t css 15 ns minimum sclk_pwr0 low to rising edge of cs _dev setup time t hcs 60 ns minimum sclk_pwr0 low after rising edge of cs _dev hold time t hs 15 ns minimum data valid to sclk_ pwr0 rising-edge setup time t ds 30 ns minimum data valid to sclk_ pwr0 rising-edge hold time t dh 15 ns minimum sclk_pwr0 high pulse width t ch 120 ns minimum sclk_pwr0 low pulse width t cl 120 ns minimum cs _dev high pulse width t csh 120 ns maximum transition time from falling-edge of cs _dev to valid gpo2_mod t csg c l = 10pf load capacitance from gpo2_mod to dgnd 400 ns maximum transition time from falling edge of sclk_pwr0 to valid gpo2_mod t cg c l = 10pf load capacitance from gpo2_mod to dgnd 400 ns
8 ______________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter figure 1. spi timing diagram typical operating characteristics ( typical application circuit , 50 i system impedance, v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.1v to 3.6v, f rf = 280mhz to 450mhz, f xtal = 16mhz, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.7v, t a = +25 n c, pa matched for optimum output power, unless otherwise noted. supply current and output power are greatly dependent on board layout and paout match.) t csh t sc cs_dev sclk_pwro sdi_pwr1 gpo2_mod t csg t cg t hs t hcs t css t ds t dh t cl t ch MAX7060 toc01 supply current (ma) 12 14 16 18 20 22 24 26 28 30 10 supply current vs. supply voltage (f rf = 315mhz, pa on) v dd (v) 3.3 3.0 2.7 2.4 2.1 3.6 papwr = 0x16 papwr = 0x1e t a = +125c t a = +85c t a = +25c 3v mode t a = -40c -40c +125c MAX7060 toc02 supply current (ma) 12 14 16 18 20 22 24 26 28 30 10 supply current vs. supply voltage (f rf = 315mhz, pa on) v dd (v) 5.3 5.1 4.9 4.7 4.5 5.5 t a = -40c t a = +25c t a = +85c t a = +125c 5v mode papwr = 0x16 papwr = 0x1e -40c +125c MAX7060 toc03 supply current (ma) 3 4 5 6 7 8 2 supply current vs. supply voltage (f rf = 315mhz, pa off) v dd (v) 3.3 3.0 2.7 2.4 2.1 3.6 t a = -40c t a = +25c t a = +125c t a = +85c 3v mode supply current vs. supply voltage (f rf = 433.92mhz, pa on) MAX7060 toc04 v dd (v) supply current (ma) 3.3 3.0 2.7 2.4 16 18 20 22 24 26 28 30 32 34 36 38 14 2.1 3.6 t a = -40c t a = +25c t a = +85c t a = +125c 3v mode papwr = 0x16 papwr = 0x1e -40c +125c MAX7060 toc05 supply current (ma) 18 20 22 24 26 28 30 32 34 36 16 supply current vs. supply voltage (f rf = 433.92mhz, pa on) v dd (v) 5.3 5.1 4.9 4.7 4.5 5.5 t a = -40c t a = +25c t a = +85c t a = +125c 5v mode papwr = 0x16 papwr = 0x1e -40c +125c MAX7060 toc06 supply current (ma) 3 4 5 6 7 8 2 supply current vs. supply voltage (f rf = 433.92mhz, pa off) v dd (v) 3.3 3.0 2.7 2.4 2.1 3.6 t a = -40c t a = +25c t a = +125c t a = +85c 3v mode
_______________________________________________________________________________________ 9 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter typical operating characteristics (continued) ( typical application circuit , 50 i system impedance, v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.1v to 3.6v, f rf = 280mhz to 450mhz, f xtal = 16mhz, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.7v, t a = +25 n c, pa matched for optimum output power, unless otherwise noted. supply current and output power are greatly dependent on board layout and paout match.) pa power vs. pa power code, 433.92mhz MAX7060 toc15 pa power code (decimal) p out (dbm) 30 25 5 10 15 20 -15 -10 -5 0 5 10 15 20 -20 0 35 v dd = 2.7v v dd = 2.1v v dd = 3.6v 3v mode supply current vs. pa power code, 315mhz MAX7060 toc14 pa power code (decimal) supply current (ma) 30 25 20 15 10 5 10 15 20 25 30 5 0 35 5v mode v dd = 5.5v v dd = 5v v dd = 4.5v pa power vs. pa power code, 315mhz MAX7060 toc13 pa power code (decimal) p out (dbm) 30 25 5 10 15 20 -12 -8 -4 0 4 8 12 16 -16 0 35 5v mode v dd = 5.5v v dd = 5v v dd = 4.5v supply current vs. pa power code, 315mhz MAX7060 toc12 pa power code (decimal) supply current (ma) 30 25 20 15 10 5 5 10 15 20 25 30 35 0 0 35 v dd = 2.7v v dd = 2.1v v dd = 3.6v 3v mode pa power vs. pa power code, 315mhz MAX7060 toc11 pa power code (decimal) p out (dbm) 30 25 20 15 10 5 -10 -5 0 5 10 15 20 -15 0 35 v dd = 2.7v v dd = 2.1v v dd = 3.6v 3v mode MAX7060 toc10 5 7 9 11 13 15 3 v dd (v) 5.3 5.1 4.9 4.7 4.5 5.5 t a = -40c t a = +125c t a = +25c t a = +25c t a = +85c t a = -40c t a = +85c t a = +125c output power vs. supply voltage (f rf = 433.92mhz, pa on) p out (dbm) 5v mode papwr = 0x16 papwr = 0x1e output power vs. supply voltage (f rf = 433.92mhz, pa on) MAX7060 toc09 p out (dbm) 4 6 8 10 12 14 16 2 v dd (v) 3.3 3.0 2.7 2.4 2.1 3.6 t a = -40c t a = +85c t a = -40c t a = +125c t a = +125c t a = +85c t a = +25c t a = +25c 3v mode papwr = 0x16 papwr = 0x1e MAX7060 toc08 7 9 11 13 15 17 5 v dd (v) 5.3 5.1 4.9 4.7 4.5 5.5 t a = -40c t a = -40c t a = +25c t a = +85c t a = +25c t a = +85c t a = +125c t a = +125c output power vs. supply voltage (f rf = 315mhz, pa on) p out (dbm) 5v mode papwr = 0x16 papwr = 0x1e output power vs. supply voltage (f rf = 315mhz, pa on) MAX7060 toc07 p out (dbm) 6 8 10 12 14 16 18 4 v dd (v) 3.3 3.0 2.7 2.4 2.1 3.6 t a = -40c t a = +85c t a = +85c t a = -40c t a = +25c t a = +125c t a = +125c t a = +25c 3v mode papwr = 0x16 papwr = 0x1e
10 _____________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter typical operating characteristics (continued) ( typical application circuit , 50 i system impedance, v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.1v to 3.6v, f rf = 280mhz to 450mhz, f xtal = 16mhz, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.7v, t a = +25 n c, pa matched for optimum output power, unless otherwise noted. supply current and output power are greatly dependent on board layout and paout match.) reference spur magnitude vs. supply voltage MAX7060 toc21 supply voltage (v) reference spur magnitude (dbc) 3.3 3.0 2.7 2.4 -46 -44 -42 -40 -48 2.1 3.6 433.92mhz 315mhz 3v mode phase noise vs. offset frequency (f rf = 433.92mhz, t a = +25c, v dd = 2.7v, pa code = 0x19) MAX7060 toc20 offset frequency (hz) phase noise (dbc/hz) 1m 100k 10k -120 -110 -100 -90 -80 -70 -60 -50 -130 1k 10m phase noise vs. offset frequency (f rf = 315mhz, t a = +25c, v dd = 2.7v, pa code = 0x19) MAX7060 toc19 offset frequency (hz) phase noise (dbc/hz) 1m 100k 10k -130 -120 -110 -100 -90 -80 -70 -60 -140 1k 10m supply current vs. pa power code, 433.92mhz MAX7060 toc18 pa power code (decimal) supply current (ma) 30 25 20 15 10 5 10 15 20 25 30 35 5 0 35 5v mode v dd = 5.5v v dd = 5v v dd = 4.5v pa power vs. pa power code, 433.92mhz MAX7060 toc17 pa power code (decimal) p out (dbm) 30 25 20 15 10 5 -10 -5 0 5 10 15 -15 0 35 5v mode v dd = 5.5v v dd = 5v v dd = 4.5v supply current vs. pa power code, 433.92mh z MAX7060 toc16 pa power code (decimal) supply current (ma) 30 25 15 20 10 5 5 10 15 20 25 30 35 40 45 0 0 35 v dd = 3.6v v dd = 2.7v v dd = 2.1v 3v mode
______________________________________________________________________________________ 11 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter pin configuration/functional diagram typical operating characteristics (continued) ( typical application circuit , 50 i system impedance, v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.1v to 3.6v, f rf = 280mhz to 450mhz, f xtal = 16mhz, t a = -40 n c to +125 n c, unless otherwise noted. typical values are at v dd5 = v gpovdd = v avdd = v dvdd = v pavdd = 2.7v, t a = +25 n c, pa matched for optimum output power, unless otherwise noted. supply current and output power are greatly dependent on board layout and paout match.) fsk spectrum (f rf = 315mhz, +25c, v dd = 2.7v, pa code = 0x19 50khz deviation, 4khz square wave on din) MAX7060 toc23 f rf (mhz) p out (dbm) 315.3 315.1 314.9 314.7 -20 -10 0 10 20 -30 314.5 315.5 rbw = 10khz vbw = 10khz reference spur magnitude vs. supply voltage MAX7060 toc22 supply voltage (v) reference spur magnitude (dbc) 5.3 5.1 4.9 4.7 -46 -44 -42 -40 -48 4.5 5.5 433.92mhz 315mhz 5v mode tqfn 19 20 21 22 1 2 3 4 5 6 18 17 16 15 14 13 23 24 12 11 10 9 8 7 cs_dev sclk_pwr0 sdi_pwr1 enable n.c. gpo2_mod gpo1 dvdd gpovdd freq0 freq1 xtal1 xtal2 n.c. v dd5 pavout din rout paout pavdd n.c. freq2 lshdn avdd crystal oscillator serial interface, configuration, and control 3 5 pfd frequency divider ? modulator charge pump loop filter voltage regulator pulse shaping pa power control exposed pad gnd ask data /k vco pa + MAX7060
12 _____________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter pin description pin name function 1 gpo2_mod (spi mode/manual mode) digital input/output. gpo2 output in spi mode. acts as an spi data output when cs _dev is low. ask (0)/fsk (1) modulation select input in manual mode. this pin is internally pulled down in manual mode. 2 gpo1 general-purpose output 1. in spi mode, this pin can output many internal status signals. in manual mode, this pin outputs the synthesizer lock-detect (lockdet) signal . 3 dvdd digital-supply voltage input. bypass to gnd with a 0.01 f f capacitor as close as possible to the pin. 4 gpovdd power-supply voltage input for gpos and esd-protection devices. bypass to gnd with a 0.01 f f capacitor as close as possible to the pin. 5 freq0 frequency-select pin 0 in manual mode. internally pulled down. freq0 = freq1 = freq2 = 0 for spi mode. 6 freq1 frequency-select pin 1 in manual mode. internally pulled down. freq0 = freq1 = freq2 = 0 for spi mode. 7 freq2 frequency-select pin 2 in manual mode. internally pulled down. freq0 = freq1 = freq2 = 0 for spi mode. 8 lshdn low-power shutdown current-select digital input. turns off internal por circuit and disables pullup/pulldown currents. must be driven low for normal operation in 3v mode. functional only in 3v mode. connect to gnd in 5v mode. 9, 15, 24 n.c. no connection. internally not connected. leave unconnected. 10 paout power amplifier output. requires a pullup inductor to pavout, which can be part of the output- matching network to an antenna. 11 pavdd power amplifier predriver power-supply input. bypass to gnd with a 680pf capacitor and a 0.01 f f as close as possible to the pin. 12 rout envelope-shaping resistor connection. see the typical application circuits and the ask envelope shaping sections for details. 13 pavout power amplifier power-control output. controls the transmitted power. connect to pa pullup inductor. bypass to ground with 680pf capacitor. 14 v dd5 supply voltage input. bypass to ground with 0.01 f f and 0.1 f f capacitors. 16 avdd analog supply voltage and regulator output. bypass to gnd with 0.1 f f and 0.01 f f capacitors as close as possible to the pin. 17 xtal2 crystal input 2. xtal2 can be driven from an ac-coupled external reference. 18 xtal1 crystal input 1. ac-couple to gnd if xtal2 is driven from an ac-coupled external reference. 19 cs _dev (spi mode/manual mode) serial peripheral interface (spi) active-low chip-select input. fsk frequency-deviation input (0 = low deviation, 1 = high deviation) in manual mode. internally pulled up. 20 sdi_pwr1 (spi mode/manual mode) spi data input in spi mode. power-control msb input in manual mode. internally pulled down. 21 sclk_pwr0 (spi mode/manual mode) spi clock input in spi mode. power-control lsb input in manual mode. internally pulled down. 22 enable enable digital input. all internal circuits (except the pa in ask mode) are enabled on the rising edge of enable. internally pulled down. 23 din transmit data digital input. internally pulled down. ep exposed pad. solder evenly to the boards ground plane for proper operation.
______________________________________________________________________________________ 13 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter detailed description the MAX7060 is power and frequency programmable from 280mhz to 450mhz. the MAX7060 has an internal transmit power control that can be programmed over a 28db power range. the MAX7060 has tuning capacitors at the output of the power amplifier (pa) to ensure high- power efficiency at various programmable frequencies with a single matching network. the crystal-based architecture of the MAX7060 elimi - nates many of the common problems with saw trans - mitters by providing greater modulation depth, faster frequency settling, tighter tolerance of the transmit fre - quency, and reduced temperature dependence. in par - ticular, the tighter transmit frequency tolerance means that a superheterodyne receiver with a narrower if bandwidth (therefore lower noise bandwidth) can be used. the payoff is better overall receiver performance when using a superheterodyne receiver such as the max1473, max1471, max7033, max7034, max7036, and max7042. the MAX7060 can be configured in either spi or manual mode, where the transmitter can easily be configured without the need of an spi interface. in the 3v operation, the MAX7060 can be put in a low- power shutdown mode by pulling enable low and lshdn high. in this mode, all the blocks are shut down including power-on reset (por). all the MAX7060 reg - isters must be reprogrammed after lshdn is asserted high. in the 5v operation, the low-power shutdown mode is not available, and lshdn should be connected to gnd. frequency programming the MAX7060 is a crystal-referenced phased-locked- loop (pll) vhf/uhf transmitter that transmits data over a wide frequency range. the internal vco can be tuned from 280mhz to 450mhz and controlled by a single crystal to cover up to a 1.47:1 carrier-frequency range. the transmit frequency is set by the crystal frequency and the programmable divider in the pll; the program - mable pll divide ratios can be set anywhere from 19 to 28, which means that with a crystal frequency of 15mhz, the output is 285mhz to 420mhz. with a crystal frequen - cy of 16mhz, the output is 304mhz to 448mhz. the MAX7060 has an internal variable capacitor con - nected across the pa output. this capacitor can be pro - grammed to maintain high-efficiency transmission at any frequency within a 1.47 to 1 (28/19) tuning range. this means that it is possible to change the frequency and retune the antenna to the new frequency in a very short time. the combination of rapid antenna-tuning ability with rapid synthesizer tuning makes the MAX7060 a true frequency-agile transmitter. the tuning capacitor has a nominal resolution of 0.25pf, from 0 to 7.75pf. the MAX7060 supports data rates up to 100kbps nrz in ask mode and 140kbps nrz in fsk mode. in fsk mode, the frequency deviation corresponding to bit 1 and bit 0 can be set as low as q 2khz, and as high as q 100khz. the frequency deviation is fully programmable in spi mode, and can be selected either as q 16khz or q 50khz in manual mode. power amplifier (pa) the pa of the MAX7060 is a high-efficiency, open-drain switching-mode amplifier. in a switching-mode amplifier, the gate of the final-stage fet is driven with a very sharp 25% duty-cycle square wave at the transmit frequency. this square wave is derived from the synthesizer circuit. when the matching network is tuned correctly, the output fet resonates the attached tank circuit with a minimum amount of power dissipated in the fet. with a proper output-matching network, the pa can drive a wide range of antenna impedances, which include a small-loop pcb trace and a 50 i antenna. the output-matching network suppresses the carrier harmonics and transforms the antenna impedance to an optimal impedance at paout, which is from 60 i to 125 i . when the output-matching network is properly tuned, the MAX7060 transmits power with a high overall efficiency. the efficiency of the pa itself is approximately 50%. transmitter power control the transmitter power of the MAX7060 can be set in approximately 1db steps (spi mode) to produce a maxi - mum output power level of +14dbm with a 5v supply. if a battery is used as the supply, the maximum output power level varies from +15dbm at 3.6v to +10dbm at 2.1v. the minimum power level is -14dbm for both 5v and battery supplies. the maximum transmitter power (and the transmitter current) can be lowered by increas - ing the load impedance on the pa. four fixed power levels are available in manual mode. when a 5v supply is used, the v dd5 and gpovdd pins are connected to the 5v supply. avdd is the output of an internal voltage regulator and must be connected externally to dvdd and pavdd. the pavout pin is connected to the paout pin through a biasing inductor. pavout is not connected to any of the power-supply
14 _____________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter pins. connecting pavout to paout enables tx power control. in spi mode, there are 31 power-control settings in approximately 1db monotonic steps. in manual mode, four power-control settings are available. ask envelope shaping the MAX7060 has two types of ask envelope shaping: digital shaping (spi mode only) and analog shaping through an internal resistor. envelope shaping results in a smaller spectral width of the modulated pa output signal. in digital shaping, the user can choose the final tx power setting, the power step size in units as small as 1db, and the step-time interval in units as small as 0.25 f s, when a 16mhz crystal is used. this shaping method causes the pa to transmit an envelope that rises linearly in decibels (exponentially in power) with time. digital shaping is pro - grammed through the spi. the analog shaping mode uses an internal envelope- shaping resistor for ask modulation, which connects between pavout and rout. when connected to the pa pullup inductor, the envelope-shaping resistor slows the turn-on/turn-off time of the pa. the user can choose three turn-on/turn-off times through the spi. a single turn- on/turn-off time is set internally in manual mode. variable capacitor the MAX7060 has an internal set of capacitors that can be switched in and out to present different capacitor values at the pa output. the capacitors are connected from the pa output to ground. this allows changing the tuning network along with the synthesizer divide ratio each time the transmitted frequency changes, making it possible to maintain maximum transmitter power while moving rapidly from one frequency to another. in spi mode, the variable capacitor is programmed through a register setting. in manual mode, the capacitor setting is programmed through the din pin. the tuning capacitor has a nominal resolution of 0.25pf, from 0 to 7.75pf. phase-locked loop (pll) the MAX7060 utilizes a fully integrated fractional-n pll for its frequency synthesizer. all pll components, including the loop filter, are included on-chip. two loop bandwidths can be selected in spi mode. the synthe - sizer has 16-bit fractional-n topology (4 bits integer, 12 bits fractional) with a divide ratio that can be set from 19 to 28, allowing the transmit frequency to be adjusted in increments of f xtal /4096. the fractional-n architecture also allows exact fsk frequency deviations to be programmed, completely eliminating the problems associated with generating fre - quency deviations by crystal oscillator pulling. fsk deviations as low as q 2khz and as high as q 100khz can be set in spi mode. in manual mode, the user can select between q 16khz and q 50khz. the integer and fractional portions of the pll divider ratio set the transmit frequency. this is done by load - ing the divide-ratio registers in spi mode, or selecting the states of the three frequency-control pins (freq2, freq1, freq0) in manual mode. for ask modulation, the two 8-bit center-frequency registers (fce[15:0]) are loaded with the divide ratio determined by the center frequency and the crystal. for fsk modulation, the two 8-bit high (mark) frequency registers (fhi[15:0]) and the two 8-bit low (space) frequency registers (flo[15:0]) are loaded. the divide ratios for the fhi and flo are deter - mined by the center frequency, the frequency deviation, and the crystal frequency. examples of typical settings for ask and fsk modulation are given in the spi mode settings section. crystal (xtal) oscillator the xtal oscillator in the MAX7060 is designed to pres - ent a capacitance of approximately 6pf between the xtal1 and xtal2 pins. in most cases, this corresponds to a 8pf load capacitance applied to the external crystal when typical pcb parasitics are added. it is very impor - tant to use a crystal with a load capacitance equal to the capacitance of the MAX7060 crystal oscillator plus pcb parasitics. if a crystal designed to oscillate with a differ - ent load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. a crystal designed to oper - ate at a higher load capacitance than the value specified for the oscillator is always pulled higher in frequency. adding capacitance to increase the load capacitance on the crystal increases the startup time and can prevent oscillation altogether. in actuality, the oscillator pulls every crystal. the crystals natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified fre - quency. this pulling is already accounted for in the specification of the load capacitance.
______________________________________________________________________________________ 15 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter additional pulling can be calculated if the electrical parameters of the crystal are known. the frequency pull - ing is given by: 6 m p case load case spec c 1 1 f 10 2 c c c c ? ? = ? ? ? + + ? ? where: f p is the amount the crystal frequency pulled in ppm c m is the motional capacitance of the crystal c case is the case capacitance c spec is the specified load capacitance c load is the actual load capacitance when the crystal is loaded as specified (i.e., c load = c spec ), the frequency pulling equals zero. general-purpose output (gpo)/clock outputs the MAX7060 has two gpo pins in spi mode (gpo2_ mod and gpo1) and one gpo in manual mode (gpo1). the gpo1 pin can serve as a clock for a microprocessor or any other gpo function in spi mode. in manual mode, this pin outputs the synthesizer lock-detect (lockdet) status, after which the user can send data through the din pin. the gpo2_mod pin acts as the spi data output when the cs _dev pin is low, in spi mode. when cs _dev is high, it acts as a gpo that can output various internal signals, such as the synthesizer lock detect (lockdet). in spi mode, the output clock that can be routed through gpo1 is a divided version of the crystal frequency. the divide ratio is set through the MAX7060 registers, and the divide settings are 1 (no division), 2, 4, 8, or 16. an external buffer is recommended to drive external devices if divide settings of 1, 2, and 4 are selected. serial peripheral interface (spi) the MAX7060 utilizes a 4-wire spi protocol for pro - gramming its registers, configuring and controlling the operation of the whole transmitter. for spi operation, the freq2, freq1, and freq0 pins must be reset to 0. the following digital i/os control the operation of the spi: cs _dev active-low spi chip select sdi_pwr1 spi data input sclk_pwr0 spi clock gpo2_mod spi data output figure 2 shows the general timing diagram of the spi protocol. any number of 8-bit data bursts (data 1, data 2 data n) can be sent within one cycle of the cs _dev pin, to allow for burst-write or burst-read operations. the spi data output signal is routed through the gpo2_mod pin when cs _dev is low. figure 2. spi format di7 di6 di5 di4 di3 di2 di1 di0 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 do7 do6 do5 do4 do3 do2 do1 do0 sclk_pwr0 sdi_pwr1 gpo2_mod cs_dev data 1 data n
16 _____________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter spi commands the following commands are implemented in the MAX7060: write: within the same cs _dev cycle, a write command is implemented as follows: sdi_pwr1: <0x01> with this command, data 1 is written to the address given by , data 2 is written to , and so on. read: within the same cs _dev cycle, a read command is implemented as follows: sdi/pwr1: <0x02>

<0x00> gpo2_mod: <0xxx> <0xxx> with this command, all the registers can be read within the same cycle of cs _dev. the addresses can be given in any order. figure 3. spi write command format figure 4. spi read command format a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d0 sclk_pwr0 sdi_pwr1 cs_dev write command (0x01) initial address (a[7:0]) data 1 data n a7 sclk_pwr0 sdi_pwr1 gpo2_mod cs_dev read command (0x02) address 1 address 2 address n 0x00 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 a7 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d0 d0 d7 data 1 data 2 data n
______________________________________________________________________________________ 17 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter read all: within two cs _dev cycles, the read-all command is implemented as follows: cs _dev cycle 1 cs _dev cycle 2 sdi_pwr1: <0x03>

<0x00> <0x00> <0x00> ... <0x00> gpo2_mod: ... reset: an spi reset command is implemented as follows: sdi_pwr1: <0x04> an internal active-low master reset pulse is generated, from the falling edge of the last sclk_pwr0 signal to the falling edge of the following cs _dev signal (t hcs + t csh ). figure 5. spi read-all command format figure 6. spi reset command format a7 sclk_pwr0 gpo2_mod sdi_pwr1 cs_dev read-all command (0x03) address n d7 d6 d5 d4 d3 d2 d1 d0 d7 d0 d0 d7 data n data n + 1 a6 a5 a4 a3 a2 a1 a0 data n + n sclk_pwro cs_dev internal reset pulse reset command (0x04) sdi_pwr1
18 _____________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter applications information spi mode settings ask carrier frequency when the MAX7060 is in ask mode, only the carrier frequency needs to be set. to do this, the user calcu - lates the divide ratio based on the carrier frequency and crystal frequency. the example below shows how to determine the correct value to be loaded into the carrier- frequency registers (fce[15:0]). due to the nature of the transmit pll frequency divider, a fixed offset of 16 must be subtracted from the trans - mit pll divider ratio for programming the MAX7060s transmit-frequency registers. to determine the value to program the MAX7060s transmit-frequency registers, convert the decimal value of the following equation to the nearest hexadecimal value: rf xtal f 16 4096 f ? ? ? = ? ? ? ? decimal value to program the transmit-frequency registers assume the ask transmit frequency = 315mhz and f xtal = 16mhz. in this example, the rounded decimal value is 15,104 or 0x3b00. the upper byte (0x3b) is loaded into the fcenter0 register (fce[15:8]) and the lower byte (0x00) is loaded into the fcenter1 register (fce[7:0]). fsk mark and space frequencies when the MAX7060 is in fsk mode, two frequencies need to be set: the mark (logical 1) frequency and the space (logical 0) frequency. in most cases, the two fre - quencies are above and below the carrier frequency by the deviation frequency. therefore, the user needs to calculate the divide ratio for both frequencies and load them into four registers. the procedure for calculating the register settings is the same as it is for calculating the carrier frequency. the example below shows how to determine the register settings for the mark and space frequencies when the frequency deviation is 50khz (100khz between mark and space). assume that, for an fsk transmitter centered at 433.92mhz, the mark frequency is 433.97mhz, the space frequency is 433.87mhz, and the crystal fre - quency is 16mhz. in this example, the rounded decimal value for the mark frequency is 45,560 or 0xb1f8. for the space frequency, the rounded decimal value is 45,535 or 0xb1de. the mark setting is loaded into the fhigh0 and fhigh1 registers (fhi[15:0]), and the space setting is loaded into the flow0 and flow1 registers (flo[15:0]). transmit power settings (5v supply) the output power level is set by entering a 5-bit value into the papwr register (papwr[4:0]). the highest setting (30dec or 0x1e) corresponds to the highest transmit - ted power level. each step is slightly less than 1db (approximately 0.95db), with the lowest setting produc - ing a transmitted power 28db lower than the highest. the highest transmitted power depends on the load presented to the pa output. a 50 i or 60 i load produces an output power level of +14dbm to +15dbm when the highest papwr[4:0] setting (0x1e) is applied. increasing the load resistance reduces the output power level. reducing the setting by one step reduces the power by approximately 1db, and the minimum transmitted power is still about 28db below the maximum. for example, if the load resistance is increased to the point where the output power for the maximum setting (0x1e) is +10dbm, then the minimum setting (0x00) produces an output power of about -18dbm. transmit power settings (3v supply) the output power level in 3v operation is set the same way as in 5v operation, but the variation in the 3v sup - ply (the specified range is 2.1v to 3.6v) affects the maximum power that can be transmitted. if the supply is 3.6v, then the maximum papwr[4:0] setting (0x1e) still produces a +14dbm to +15dbm transmitted power level. as the supply voltage decreases, the transmitted power at the highest settings is compressed, so that the top setting and an increasing number of the lower settings produce the same transmitted power, which is lower than the +14dbm to +15dbm achieved with a 3.6v supply. for example, a 2.7v supply produces a maximum transmitter power of +12dbm to +13dbm, and the papwr register settings from 0x1b to 0x1e (27dec to 30dec) produce the same transmitter power. below this compressed range, the power settings give the same power levels that they would give with a 5v supply. at the lowest supply level of 2.1v, the maximum setting produces a maximum transmitter power of +10dbm, and the papwr register settings from 0x19 to 0x1e (25dec to 30dec) produce the same transmitter power. the effect of a lower supply voltage reduces the maximum power and the adjustment range. the power at the lowest set - ting remains unchanged. the transmitted power using a 3v supply can be set higher than the levels described in the paragraph above by connecting paout directly to pavdd and discon - necting (leave open) the pavout pin. the tradeoff of this connection is that there is no transmit power adjustment.
______________________________________________________________________________________ 19 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter ask amplitude shaping at data rates higher than 30kbps manchester (60kbps nrz), it may be necessary to shape the ask transmitter pulses to reduce the occupied bandwidth of the trans - mitted signal to comply with government regulations (fcc in the u.s., etsi in europe). there is no shaping of the fsk modulation. the MAX7060 has two forms of amplitude shaping: digital and analog. digital amplitude shaping the digital shaping feature allows the user to choose a linear stairstep function to increase and decrease the power when the pa is turned on and off for an ask bit interval. there are three registers that control the digital amplitude shaping settings. the first setting is the final power of the pa when the pulse reaches its maximum (papwr register). the second setting is the amplitude change, in decibels, for each step, which is the vertical axis of the stairstep (pastep register). the third setting is the time interval of each step, which is the horizontal axis of the stairstep (tstep register). the final power set - ting (decimal 0 to 30 in increments of 1db) is entered in the papwr register. the amplitude step (decimal 0 to 30 in increments of 1db) is entered in the pastep register. the time interval (decimal 0 to 60/f xtal in increments of 4/f xtal ) is entered in the tstep register. for example, to shape an 80kbps nrz data stream (12.5 f s bit interval), the user might choose a maximum power level of 0x1e (30dec), an amplitude step of 5db, and a time interval of 0.5 f s assuming a crystal frequency of 16mhz. this would produce an ask pulse that ramps up in 3 f s, lev - els off for 9.5 f s, and ramps down in 3 f s. because the amplitude steps are in decibels, the shape of the pulse rise and fall is exponential on a linear display (an oscil - loscope, for instance). because most ask receivers use a logarithmic amplitude detector, the demodulated pulse has a linear ramp shape. the digital shaping is disabled when the tstep register is 0x00. analog amplitude shaping to use the analog shaping feature, the user must con - nect the bias inductor to the rout pin instead of directly to the pavout pin. this places a mos resistor between pavout and paout, which slows down the applica - tion of the pavout voltage to the drain of the pa fet when the pa is turned on. there are three settings in the anshp[1:0] bits in the conf0 register for the rate at which the pulse ramps up: anshp[1:0] = 11 is the fastest (approximately 1 f s); anshp[1:0] = 10 is approximately 1.5 f s and anshp[1:0] = 01 is approximately 3 f s; and anshp[1:0] = 00 setting opens the connection between paout and pavout, disabling the analog amplitude shaping feature. tuning capacitor settings the internal variable shunt capacitor, which can be used to match the pa to the antenna with changing transmitter frequency, is controlled by setting the 5-bit cap vari - able in the registers. this allows for 32 levels of shunt capacitance control. since the control of these 5 bits is independent of the other settings, any capacitance value can be chosen at any frequency, making it possible to maintain maximum transmitter efficiency while moving rapidly from one frequency to another. the internal tun - ing capacitor adds 0 to 7.75pf to the pa output in 0.25pf steps. the pa output capacitance at the minimum cap setting is approximately 4.5pf. figure 7. digital amplitude shaping timing diagram din papwr = 0x1e (30dec) 0 12.5s 12.5s tstep = 0x2 (0.5s) tstep = 0x2 (0.5s) pastep = 0x05 (5db) pastep = 0x05 (5db)
20 _____________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter register details the following tables provide information on the MAX7060 registers. table 1. register summary table 2. configuration registers register address description ident 0x00 read-only register used for identification purpose. the content of this register is always 0xa6. conf0 0x01 configuration 0 register. controls the gpo1 boost mode, pll bandwidth, analog shaping, crys - tal clock output, and the modulation mode (ask/fsk). conf1 0x02 configuration 1 register. controls the clock output frequency divider and the capacitance at the pa output. conf2 0x03 configuration 2 register. controls the emulation mode. ioconf0 0x04 io configuration 0 register. selects the status register bus for spi operation. ioconf1 0x05 io configuration 1 register. selects the outputs of gpo1 and gpo2_mod pins. tstep 0x06 digital shaping time step register. controls the time step in the digital shaping. pastep 0x07 digital shaping power step register. controls the power step in the digital shaping. papwr 0x08 final power register. controls the final output power. fhigh0 0x09 high-frequency 0 register (upper byte). sets the high frequency in fsk transmission. fhigh1 0x0a high-frequency 1 register (lower byte). sets the high frequency in fsk transmission. fcenter0 0x0b center-frequency 0 register (upper byte). sets the carrier frequency in ask transmission. fcenter1 0x0c center-frequency 1 register (lower byte). sets the carrier frequency in ask transmission. flow0 0x0d low-frequency 0 register (upper byte). sets the low frequency in fsk transmission. flow1 0x0e low-frequency 1 register (lower byte). sets the low frequency in fsk transmission. fload 0x0f frequency-load register. performs the frequency-load function. enablereg 0x10 enable register. register equivalent of enable pin. datareg 0x11 datain register. register equivalent of din pin. status 0x12 status register register address data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode ident 0x00 1 0 1 0 0 1 1 0 r conf0 0x01 gp1bst pllbw anshp_1 anshp_0 clksby clkout mode r/w conf1 0x02 ckdiv_2 ckdiv_1 ckdiv_0 cap_4 cap_3 cap_2 cap_1 cap_0 r/w conf2 0x03 fixed fxmode fxpwr_1 fxpwr_0 fxhdev fxfrq_2 fxfrq_1 fxfrq_0 r/w ioconf0 0x04 tmux_2 tmux_1 tmux_0 r/w ioconf1 0x05 gp2s_2 gp2s_1 gp2s_0 gp1s_2 gp1s_1 gp1s_0 r/w tstep 0x06 tstep_3 tstep_2 tstep_1 tstep_0 r/w pastep 0x07 pastp_4 pastp_3 pastp_2 pastp_1 pastp_0 r/w papwr 0x08 papwr_4 papwr_3 papwr_2 papwr_1 papwr_0 r/w fhigh0 0x09 fhi_15 fhi_14 fhi_13 fhi_12 fhi_11 fhi_10 fhi_9 fhi_8 r/w fhigh1 0x0a fhi_7 fhi_6 fhi_5 fhi_4 fhi_3 fhi_2 fhi_1 fhi_0 r/w fcenter0 0x0b fce_15 fce_14 fce_13 fce_12 fce_11 fce_10 fce_9 fce_8 r/w fcenter1 0x0c fce_7 fce_6 fce_5 fce_4 fce_3 fce_2 fce_1 fce_0 r/w
______________________________________________________________________________________ 21 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter table 2. configuration registers (continued) table 3. identification (ident) register (address: 0x00) table 4. configuration 0 (conf0) register (address: 0x01) table 5. configuration 1 (conf1) register (address: 0x02) table 6. crystal divide settings for clock output register address data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode flow0 0x0d flo_15 flo_14 flo_13 flo_12 flo_11 flo_10 flo_9 flo_8 r/w flow1 0x0e flo_7 flo_6 flo_5 flo_4 flo_3 flo_2 flo_1 flo_0 r/w fload 0x0f hop r/w enablereg 0x10 enable r/w datareg 0x11 datain r/w status 0x12 status_7 status_6 status_5 status_4 status_3 status_2 status_1 status_0 r bit name function 7:0 ident read-only register used for identification purpose. the content of this register is always 0xa6. bit name function 6 gp1bst 0 = normal gpo1 output driver 1 = extended driving capability on gpo1 5 pllbw pll bandwidth setting, low (0) = 300khz or high (1) = 600khz; 300khz is recommended for fractional-n and 600khz for fixed-n (ask mode only) 4:3 anshp[1:0] control time constants of the analog shaping anshp[1:0] rise/fall time 00 no analog shaping 01 nominal 3.0 f s rise/fall time 10 nominal 1.5 f s rise/fall time 11 nominal 1.0 f s rise/fall time 2 clksby crystal clock output enable (1) while part is in standby mode 1 clkout crystal clock output enable (1) on gpo1 output, gp1s[2:0] = 0x2 0 mode ask (0) or fsk (1) bit name function 7:5 ckdiv[2:0] 3-bit clock output frequency divider 4:0 cap[4:0] 5-bit capacitor setting ckdiv[2:0] crystal frequency divided by 000 1 001 2 010 4 011 8 1xx 16
22 _____________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter table 7. configuration 2 (conf2) register (address: 0x03) table 8. io configuration 0 (ioconf0) register (address: 0x04) bit name function 7 fixed enable (1) or disable (0) emulation mode 6 fxmode fsk (1) or ask (0) 5:4 fxpwr[1:0] output power setting fxpwr[1:0] db below p max 00 0 01 3 10 6 11 10 3 fxhdev 100khz (1) or 32khz (0) frequency deviation in fsk 2:0 fxfrq[2:0] frequency selection the combinations are same as those in manual mode. when a 16mhz crystal is used, the following fre - quency values are selected by fxfrq[2:0]. fxfrq[2:0] freq (mhz) divide ratio 000 n/a n/a 001 315.00 19.68750 010 433.62 27.10125 011 390.00 24.37500 100 418.00 26.12500 101 372.00 23.25000 110 345.00 21.56250 111 433.92 27.12000 bit name function 2:0 tmux[2:0] status register output selection bits
______________________________________________________________________________________ 23 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter where: reserved signals nock no-clock flag (1) if crystal oscillator is disabled, and (0) if clock activity is observed ckout clock output signal, according to programmed dividers (ckdiv[2:0]) lockdet pll lock-detect flag table 9. io configuration 1 (ioconf1) register (address: 0x05) table 10. ask digital shaping time step (tstep) register (address: 0x06) table 11. pa digital shaping amplitude step (pastep) register (address: 0x07) table 12. pa power (papwr) register (address: 0x08) table 13. fsk high-frequency 0 (fhigh0) register (address: 0x09) bit name function 6:4 gp2s[2:0] gpo2 output selection cs _dev bit 2 bit 1 bit 0 gpo2_mod 0 x x x spi data output 1 0 0 0 lockdet 1 0 0 1 1 0 1 0 ckout 1 0 1 1 1 1 0 0 1 1 0 1 nock 1 1 1 0 1 1 1 1 2:0 gp1s[2:0] gpo1 output selection bit 2 bit 1 bit 0 gpo1 0 0 0 lockdet 0 0 1 0 1 0 ckout 0 1 1 1 0 0 1 0 1 nock 1 1 0 1 1 1 bit name function 3:0 tstep[3:0] time interval value used in digital shaping, in increments of 4/f xtal bit name function 4:0 pastp[4:0] power step in digital shaping, in increments of 1db bit name function 4:0 papwr[4:0] final pa output power setting bit name function 7:0 fhi[15:8] 8-bit upper byte of high-frequency divider for fsk
24 _____________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter the 4 msbs of fhigh0, fhi[15:12], are the integer portion of the divider, excluding offset of 16. the 12 lsbs (fhi[11:0]) are the fractional part of the divider. table 14. fsk high-frequency 1 (fhigh1) register (address: 0x0a) table 15. ask center-frequency 0 (fcenter0) register (address: 0x0b) table 16. ask center-frequency 1 (fcenter1) register (address: 0x0c) table 17. fsk low-frequency 0 (flow0) register (address:0x0d) table 18. fsk low-frequency 1 (flow1) register (address: 0x0e) table 19. maximum and minimum values for frequency divider table 20. frequency-load (fload) register (address: 0x0f) the 4 msbs of fcenter0, fce[15:12], are the integer portion of the divider, excluding offset of 16. the 12lsbs (fce[11:0) are the fractional part of the divider. when fce[11:0] are all zeros and ask mode is selected (mode bit = 0), the pll works in the fixed-n mode, which reduces current consumption and reference spurs. set pllbw bit high (conf0 register, bit 5). for all other combina - tions, the pll works in fractional-n mode. the 4 msbs of flow0, flo[15:12], are the integer portion of the divider, excluding offset of 16. the 12 lsbs (flo[11:0]) are the fractional part of the divider. bit name function 7:0 fhi[7:0] 8-bit lower byte of high-frequency divider for fsk bit name function 7:0 fce[15:8] 8-bit upper byte of frequency divider for ask bit name function 7:0 fce[7:0] 8-bit lower byte of frequency divider for ask bit name function 7:0 flo[15:8] 8-bit upper byte of low-frequency divider for fsk bit name function 7:0 flo[7:0] 8-bit lower byte of low-frequency divider for fsk decimal value fhi[15:0], fce[15:0], flo[15:0] 12.0220 0xc05a 2.9536 0x2f42 bit name function 0 hop effectively changes the pll frequency to the ones written in registers 0x09 to 0x0e. this is a self-reset bit and is reset to zero after the operation is completed.
______________________________________________________________________________________ 25 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter reserved signals nock no-clock flag (1) if crystal oscillator is dis - abled, and (0) ic clock activity is observed ckd4 crystal clock signal divided by 4 ckd16 crystal clock signal divided by 16 ckout clock output signal, according to pro - grammed dividers (ckdiv[2:0]) enable internal enable signal (or function of the enable pin and enable bit) cap[4:0] spi mode capacitor setting frac_fxdb fractional-n mode (1) or ask fixed-n mode (0) capfxd[4:0] emulation mode variable capacitor setting notover ask digital shaping flag (1) when pa power value is different than 0 integ[3:0] fractional-n 4-bit integer value frac[11:0] fractional-n 12-bit fractional value xmit_en transmitter pa enable flag lockdet pll lock-detect flag table 21. enable (enablereg) register (address: 0x10) table 22. data input (datareg) register (address: 0x11) table 23. status (status) register (address: 0x12) table 24. status bus signals bit name function 0 enable spi equivalent of the enable pin, which should be kept low (0) if the external enable pin is used. the external enable pin should also be kept low (0) if the enable bit is used. bit name function 0 datain spi equivalent of din, where the transmitted data can be controlled through the spi interface. it should be kept low (0) if only the external din pin is used. the external din pin should also be kept low (0) if the datain bit is used. bit name function 7:0 status[7:0] read-only status register, selected through tmux[2:0] (register 0x04 ioconf0) tmux[2:0] status[7] status[6] status[5] status[4] status[3] status[2] status[1] status[0] 0 ckout ckd16 ckd4 nock 1 2 enable 3 frac_fxdb cap[4] cap[3] cap[2] cap[1] cap[0] 4 notover capfxd[4] capfxd[3] capfxd[2] capfxd[1] capfxd[0] 5 integ[3] integ[2] integ[1] integ[0] frac[11] frac[10] frac[9] frac[8] 6 frac[7] frac[6] frac[5] frac[4] frac[3] frac[2] frac[1] frac[0] 7 lockdet xmit_en
26 _____________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter manual mode settings the MAX7060 can be operated by controlling certain pins directly, thereby eliminating the need for an spi controller. there is a restricted selection of frequency and power settings, but operation is simpler. the pins that are used in manual mode are as follows: pin 1: gpo2_mod (modulation mode, 0 = ask, 1 = fsk) pins 5, 6, 7: freq0, freq1, freq2 pin 19: cs _dev (fsk deviation selection, 0 = q 16khz, 1 = q 50khz) pins 20, 21: sdi_pwr1 and sclk_pwr0 (2-pin power selection) pins 22, 23: din and enable (pa variable capacitor setting, data input, enable) to put the MAX7060 in manual mode, set any of the freq0, freq1, freq2 pins (5, 6, and 7) to logic-high. these pins are normally pulled down, so the default state of the MAX7060 is for spi operation. the settings in table 25 can be made in manual mode. frequency selection there are seven internally set fractional-n divide ratios that correspond to commonly used frequencies when a 16mhz crystal is used. notice that the MAX7060 can be operated manually at any single frequency over its 280mhz to 450mhz operat - ing range by choosing a crystal frequency and one of the divide ratios from table 25. for example, a transmitting frequency of 308mhz can be achieved by selecting the 19.68750 divide ratio and a 15.6444mhz crystal. the frequency settings in the manual mode of opera - tion were designed in a way that allows the customer to toggle only one control line between low and high states to switch between seven commonly used frequency pairs (see table 26). ask or fsk modulation reset pin 1 (gpo2_mod) to 0 for ask modulation and 1 for fsk modulation. analog shaping in ask mode is enabled by using the rout pin. the turn-on and turn-off time is fixed at approximately 1s. table 25. manual mode frequency selection table 26. manual mode frequency pair switching freq2 freq1 freq0 frequency (mhz) divide ratio 0 0 0 spi n/a 0 0 1 315.00 19.68750 0 1 0 433.62 27.10125 0 1 1 390.00 24.37500 1 0 0 418.00 26.12500 1 0 1 372.00 23.25000 1 1 0 345.00 21.56250 1 1 1 433.92 27.12000 low frequency (mhz) high frequency (mhz) freq2, freq1, freq0 315.00 433.92 001 to 111. set freq0 high, shorting freq1 and freq2, toggling 1 line. 418.00 433.92 100 to 111. set freq2 high, shorting freq1 and freq0, toggling 1 line. 433.62 433.92 010 to 111. set freq1 high, shorting freq2 and freq0, toggling 1 line. 315.00 390.00 001 to 011. set freq0 high and freq2 low, toggling freq1. 315.00 372.00 001 to 101. set freq1 low and freq0 high, toggling pin freq2. 345.00 433.92 110 to 111. set freq2 and freq1 high, toggling freq0. 390.00 433.92 011 to 111. set freq1 and freq0 high, toggling freq2.
______________________________________________________________________________________ 27 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter frequency deviation reset pin 19 ( cs _dev) to 0 for 32khz ( q 16khz) fsk deviation and 1 for 100khz ( q 50khz) fsk deviation. transmitter power set sdi_pwr1 (pin 20) and sclk_pwr0 (pin 21) to four power settings (relative to the maximum power setting). note that at battery voltages below 3v, the top two power settings are compressed and the power difference is less than 3db. pa variable capacitor setting in manual mode, capacitance can be added to the pa output for one selected frequency. this allows the user to adjust the matching network when switching between two frequencies in the manual selection table, or for switching to one frequency that is significantly different from the others in the table. the user can set the capaci - tance by resetting the enable pin to a logic-low, then selecting the frequency for which the variable capacitor is to be added from the seven possible settings, and then sending a stream of 1 to 32 pulses through the din pin. the first pulse is used to reset the internal capacitor counter and to latch the selected frequency. after the first pulse, the remaining number of pulses sent equals the variable capacitor setting. when the enable pin goes high, the capacitor setting for the specified frequency is set, so that it adds the programmed capacitance to the pa when the chosen frequency is selected. this scheme must be executed only once to set the value of the vari - able capacitor. for example, a user can operate the MAX7060 at 315mhz and 433.92mhz into a narrowband antenna by resetting the enable pin low, setting the freq0, freq1, freq2 pins to 001 (315mhz), and sending the appropriate number of pulses into the din pin, and then setting the enable pin high. when the frequency is set to 433.92mhz (or any other frequency in the table except 315mhz), no capacitance is added to the pa output. when the frequency is set to 315mhz, the pa capaci - tance increases by the programmed value. figure 8 illustrates how to set the capacitance. it begins with the enable pin pulled low. the frequency is sampled at the rising edge of the first pulse. pulses 2C11 set the capacitance code to 0x0a (10dec), which is approximately 2.5pf. the enable pin is then pulled high to finish the setting. emulation mode settings all the settings available through the manual mode of operation are also easily accessible in the spi mode. this mode is called emulation mode, whereby only writ - ing one or two registers, the whole transmitter can be configured. the conf2 register controls this mode. the emulation mode is a subset of spi mode. it gives spi users the capability to operate the part by programming just one or two registers instead of all registers. since it is still spi mode, pins 5, 6, and 7 (freq0, freq1, and freq2) must be pulled low. the conf2 register is the only register that needs to be programmed. setting bit 7 (fixed) to 1 enables this mode. bit 6 (fxmode) is equivalent to pin 1 (gpo2_mod) in manual mode. bits 5 and 4 (fxpwr[1:0]) are equivalent to pin 20 and 21 (sdi_pwr1 and sclk_pwr0) in manual mode. bit 3 (fxhdev) is equivalent to pin 19 ( cs _dev) in manual mode. bits 2, 1, and 0 (fxfrq[2:0]) are equivalent to pins 5, 6, and 7 (freq0, freq1, and freq2) in manual mode. similar to manual mode, the pa capacitor setting in the emulation mode can be done by toggling the din pin with the enable pin low. in addition, the capacitor set - ting can also be done by directly writing to the capacitor register (bits 4:0 of the conf1 register, cap[4:0]). as long as the capacitor register value is not zero, the capacitor value sent in by toggling the din pin is ignored. table 27. output power settings figure 8. variable capacitor setting timing diagram enable din freq[2:0] captured cap value x 0x1 x 0x0a cap code sdi_pwr1 sclk_pwr0 db below p max 0 0 0 0 1 3 1 0 6 1 1 10
28 _____________________________________________________________________________________ MAX7060 280mhz to 450mhz programmable ask/fsk transmitter manual mode (3v supply, shaped ask modulation, 315mhz) typical application circuits spi mode (5v supply) xtal1 gpo2_mod gpo1 dvdd gpovdd freq0 xtal2 avdd c1 c4 +3v reg +3v reg +3v reg c12 y1 c2 c3 c5 15 n.c. 16 17 18 +5v +5v c6 c7 c8 l1 c9 12 11 c10 13 3 4 5 6 14 v dd5 pavout c11 rout pavdd 9 n.c. 8 lshdn 7 freq2 10 paout cs_dev 19 1 2 20 21 22 23 24 sdi_pwr1 enable din n.c. sclk_pwr0 digital controller matching network components tx antenna freq1 MAX7060 xtal1 gpo2_mod gpo1 dvdd gpovdd freq0 xtal2 avdd c1 c4 +3v +3v c12 y1 c2 c3 c5 15 16 18 17 n.c. +3v +3v c6 c7 l1 c9 12 11 c10 13 c11 3 4 5 6 14 v dd5 pavout c8 rout pavdd 9 n.c. 8 lshdn 7 freq2 10 paout cs_dev 19 1 2 20 21 22 23 24 sdi_pwr1 enable din n.c. sclk_pwr0 digital controller freq1 MAX7060 tx antenna matching network components
______________________________________________________________________________________ 29 MAX7060 280mhz to 450mhz programmable ask/fsk transmitter component lists spi mode (5v supply) manual mode (3v supply) designation qty description c1, c4 2 not needed if crystal load capacitance is 8pf c2, c3 2 1.5nf 10%, 50v x7r ceramic capacitors (0603) murata grm188r71h152k c5, c6 2 100nf 10%, 50v x7r ceramic capacitors (0603) murata grm188r71h104k c7, c8, c9 3 220pf 5% ceramic capacitors (0603) murata grm1885c1h220ja01d c10, c11, c12 3 10nf 10%, 50v x7r ceramic capacitors (0603) murata grm188r71h103k l1 1 5% wire-wound inductor (0603) murata lqw18 series (value depends on matching network) matching network components 4 3 capacitors and 1 inductor (values depend on frequency range and antenna impedance) u1 1 maxim MAX7060atg+ y1 1 16mhz crystal crystek 17466 suntsu scx284 designation qty description c1, c4 2 not needed if crystal load capacitance is 8pf c2, c3 2 1.5nf 10%, 50v x7r ceramic capacitors (0603) murata grm188r71h152k c5, c6 2 100nf 10%, 50v x7r ceramic capacitors (0603) murata grm188r71h104k c7, c8, c9 3 220pf 5% ceramic capacitors (0603) murata grm1885c1h220ja01d c10, c11, c12 3 10nf 10%, 50v x7r ceramic capacitors (0603) murata grm188r71h103k l1 1 5% wire-wound inductor (0603) murata lqw18 series (value depends on matching network) matching network components 4 3 capacitors and 1 inductor. values depend on frequency range and antenna impedance. u1 1 maxim MAX7060atg+ y1 1 16mhz crystal crystek 17466 suntsu scx284
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 30 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. MAX7060 280mhz to 450mhz programmable ask/fsk transmitter chip information process: cmos package information for the latest package outline information and land pat - terns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suf - fix character, but the drawing pertains to the package regardless of rohs status. package type package code document no. 24 tqfn-ep t2444+3 21-0139

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